SoC DFT Engineer Full-time Job

Responsible for evaluating design readiness for scan insertion through RTL and physical design scan design rule check (DRC) tools Integration and verification of design for test (DFT) fabrics and IP within subsystems Run and evaluate scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage Run ATPG (automatic test pattern generation) analysis to ensure quality scan chain construction and meeting basic coverage goals Run and debug non-timing and SDF annotated gate level simulations Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon